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78q8392l/a03 low power ethernet coaxial transceive r page: 1 of 14 ? 2008 teridian semiconductor corporation rev 1.3 november 2008 description the 78q8392l/a03 ethernet transceiver is a replacement for the ssi/tdk/teridian 78q8392l/a02 coax line transmitter/receiver. only a single resistor value change is required for upgrading an existing 78q8392l/a02 design to the 78q8392l/a03. the device includes analog transmit and receive buffers, a 10 mhz on-board oscillator, timing logic for jabber and heartbeat functions, output drivers and bandgap reference, in addition to a current reference and collision detector. this transceiver provides the interface between the single-ended coaxial cable signals and the manchester-encoded differential logic signals. primary functional blocks include the receiver, transmitter, collision detection and jabber timer. this ic may be used in either internal or external mau environments. the 78q8392l/a03 is available in lead-free 16-pin plastic and 28-pin plcc packages. features ? very low power consumption ? compliant with ethernet ii, ieee 802.3 10base5 and 10b ase2 ? integrates all transceiver functions except signal and power isolation ? innovative design minimizes external component count and power consumption ? jabber timer function integrated on chip ? externally selectable ced heartbeat allows operation with ieee 802.3 compatible repeaters ? squelch circuitry at all inputs rejects noise ? power-on reset and test modes ? advanced bicmos process connect diagram 510 5% x 4 cd+cdC rx+ rxC tx+ tx- collision signalto dte data to dte data from dte veevee gnd rr- rr+ C9v 4 1 13 23 6 1211 78 78 txo 15 hbe 9 vee 5 cds 16 rxi 14 coax 10 downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 2 of 14 ? 2008 teridian semiconductor corporation rev 1.3 functional description the 78q8392l/a03 incorporates six basic functions of the ethernet transceiv er, including receiving, transmitting, collision signaling, collision detection, jabber timing, and the heartbeat function. refer to figure 1 for a general system block diagram. receiver functions the receiver senses signals through the rxi input, which minimizes reflections on the transmission media using a low capacitance, high resistance input buffer amplifier. the cds ground input attaches directly to the input buffer from the coaxial shield to eliminate ground loop noise. in addition to the input buffer, the receiver data path consists of an equalizer, data slicer, receiver squelch circuitry, and an output line driver. the equalizer improves the cable-induced jitter; the data slicer restores equalized received signals to fast transition signals with binary levels to drive the receiver line driver; and the receiver line driver drives the aui cable thr ough an isolation transformer that connects to the aui interface. noise on the transmission media is rejected by the receiver squelch circuitry, which determines valid data via three criteria: average dc level, pulse width and transition period. the dc voltage level is detected and compared to a set level in the receiver comparator circuit. the pulse width must be greater than 20 ns to pass the narrow pulse filter; the transition timer outputs a true level on the rx data valid line provided the time between transitions is less than about 200 ns. as long as a valid rxi signal is detected, the output li ne driver remains enabled. the transition timer disables the line driver when there are no further transitions on the data medium, and the rx+, rx- pins go to a zero differential voltage state (figure 3). transmitter functions the transmitter data path consists of a transmit input buffer, pulse-shaping filter, transmit s quelch circuitry and transmit output line driver. the self-biasing transmit input buffer receives data through an isolation transformer and translates the aui differential analog signal to a square pulse suitable for driving the pulse shaping filter. the filter outputs a correctly shaped and band limited signal to the transmit output driver, which drives the transmission medium through a high impedance current source. when the transmitter is off, the capacitance of the tr ansmit driver is isolated from the transmission media by an external diode with a low capacitance node. the shield of the transmission media serves as the ground return for the transmitter function. a transmit squelch circuit, wh ich consists of a pulse threshold detector, a pulse width detector, and a pulse duration timer, is used to suppress noise, as well as crosstalk on the aui cable. the squelch circuitry disables the transmit driver if the signal at tx+ or tx- is smaller than the pulse threshold. pulse noise is rejected by a pulse width detector that passes only pulses with durations greater than 20 ns. the pulse duration timer disables the transmit driver if no pulses are received for two-bit periods following valid pulses. at the end of a transmission, the pulse duration timer disables the transmitter and triggers the blanking timer, used to block dribble bits. collision detection a collision occurs when two or more transmitters simultaneously transmit on the transmission media. a collision is detected by comparing the average dc level of the transmission media to a collision threshold. the received signal at rxi is buffered and sent through a low pass filter, then compared in the collision threshold circuit. if the average dc level exceeds a collision threshold, a 10 mhz signal is output on the cd pins. collision signaling when collision signaling is enabled (hbe pin is high and the average dc level on rxi exceeds the collision threshold v cd ), a 10 mhz signal is sent from the cd pins through an isolation transformer to the dte. when the function is disabled, this output goes to a zero differential state. the 10 mhz signal output from the cd pins indicates a collision on the transmission media, a heartbeat function, or that the transmitter is in jabber mode. downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 3 of 14 ? 2008 teridian semiconductor corporation rev 1.3 jabber function when valid data on the tx pins is detected, the jabber timer is started. if there is valid data for more than 20 ms, a latch is set which disables the transmitter output and enables the 10 mhz output on the cd pins. the latch is reset within 0.5 seconds after the valid data is removed from the transmitter input (tx). this action resets the jabber timer and disables the 10 mhz signal on the cd pins. the tx inputs must remain inactive during the 0.5 second reset period. heartbeat function the 10 mhz cd outputs are enabled for about 1 s at approximately 1.1 s after the end of each transmission. the heartbeat signal tells the dte that the circuit is functioning. this is implemented by starting the heartbeat timer when the valid data signal indicates the end of a transmission. this function is disabled when hbe pin is tied to v ee. figure 1: 78q8392l/a03 general system block diagram data media receiver input buffer rxi cds equalizer squelch comparator lp filter squelsh threshold rx+ rx- txo transmit output driver pulse shaping filter tx+ tx- transmit input buffer bandgap reference and current reference 10 mhz osc rr+ rr- cd+ cd- slicer transition period tamer narrow pulse filter rx data valid enable slicer tx on control logic jabber timer blanking timer heart beat timer tx data valid end transmit tx disable enable tx < -250 mv tx > -250 mv comparator tx disable cd on collision threshold collision comparator buffered tx transition period timer transition end timer narrow pulse filter signal presetdetect downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 4 of 14 ? 2008 teridian semiconductor corporation rev 1.3 pin description name type description cd+*/cd- o collision output. balanced differential line driver outputs from the collision detect circuitry. the 10 mhz signal from the inte rnal oscillator is transferred to these outputs in the event of co llision, excessive transmission (jabber), or during cd heartbeat condition. these outputs are open emitters; pulldown resistors to vee are required. when operating into a 78 ? transmission line, these resistors should be 510 ? . in cheapernet applications, where the 78 ? drop cable is not used, higher resistor values (up to 1.5k ) may be used to save power. rx+*/rx- o receive output. balanced differential line dr iver outputs from the receiver. these outputs also require 510 ? pulldown resistors. tx+*/tx- i transmit input. balanced differential line re ceiver inputs to the transmitter. the common mode voltage for these inputs is determined internally and must not be externally established. signals meeti ng transmitter squelch requirements are waveshaped and output at txo. hbe i heartbeat enable. this input enables cd heartbeat when grounded or left opened, disables it when connected to vee. rr+/rr- i external resistor. a fixed 976 ? 1% resistor connected between these pins establishes internal operating currents. note: the previous generation 78q8392l/a02 used a 1k ? 1% resistor rxi i receive input. connects directly to the coaxial cable. signals meeting receiver squelch requirements are equalized for inter-s ymbol distortion, amplified, and output at rx+ and rx- pins. txo o transmit output. connects via an isolation diode to the coaxial cable. cds i collision detect sense. ground sense connecti on for the collision detect circuit. this pin should be connected separately to the sh ield to avoid ground drops from altering the receive mode collision threshold. gnd s positive supply pin. vee s negative supply pins. these pins should be connected to a large metal frame area on the pc board to handle heat dissipation, and bypassed to the gnd pin with a 0.1 f capacitor as close to the package as possible. *ieee names for cd = ci, rx = di, tx = do notes: pin type: i-input; o-output; s-power supply downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 5 of 14 ? 2008 teridian semiconductor corporation rev 1.3 electrical specifications absolute maximum ratings absolute maximum ratings indicate limits beyond whic h permanent damage may occur. continuous operation at these limits is not recommended; operations should be limited to those conditions specified under recommended operating characteristics. parameter rating supply voltage -10v input voltage 0 to v ee storage temperature -65 to 150 c soldering (reflow or dip) 235 c for 10 sec package power dissipation 1.0 watts @ 25 c dc operating characteristics 0 c t (ambient) +70 c, vee = -9v 5% parameter condition min nom max unit i ee1 supply current out of v ee pin - non-transmitting 6 8 ma i ee2 supply current out of v ee pin - transmitting 50 65 ma i rxi receive input bias current (rxi) see note 3 -2 +25 a i tdc transmit output dc current level (txo) see note 4 37 41 45 ma i tac transmit output ac current level (txo) see notes 4 & 5 28 i tdc ma v cd collision threshold (receive mode) see note 9 -1.58 -1.52 -1.404 v v od differential output voltage (rx, cd) see notes 3 & 7 550 1200 mv v oc common mode output voltage (rx, cd) see note 3, 6 & 7 -3.0 -2.5 -2.0 v v ob differential output voltage imbalance (rx, cd) see notes 3, 7 & 8 40 mv v ts transmitter squelch threshold (tx) -340 -260 -200 mv c x input capacitance (rxi) 1.2 pf r rxi shunt resistance C non-transmitting (rxi) see note 3 100 150 k ? r txo shunt resistance C transmitting (txo) see note 4 200 k ? downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 6 of 14 ? 2008 teridian semiconductor corporation rev 1.3 dc operating characteristics (continued) notes 1. currents into device pins are positive, currents out of device pi ns are negative. if not specified, voltages are referenced to ground. 2. all typical are for vee = -9v, ta = 25 c. 3. -8.55v > vee > -9.45v. 4. the voltage on txo is -4v < v(txo) < 0.0v. 5. the ac current measurement is referenced to the dc current level. 6. operating or idle state. 7. test load as shown in figure 2. 8. device measurement taken in idle state. 9. this threshold can be determined by monitoring the cd output with a dc level in rxi. figure 2: test load for cd or rx gnd 510 ? 5% rx+ or cd+ rx- or cd- ethernet xcvr v ee v oc + - 510 ? 5% v ee 50 h 1% 78 1% v ob + - v od = vcom + - downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 7 of 14 ? 2008 teridian semiconductor corporation rev 1.3 ac operating characteristics 0 c < t(ambient) < +70 c, vee = 9v 5% parameter condition min nom max unit t ron receiver startup delay (rxi to rx) 400 500 ns t rd receiver propagation delay (rxi to rx) 10 50 ns t rr differential outputs rise time (rx , cd) 4 5 ns t rf differential outputs fall time (rx , cd) 4 5 ns t rj receiver & cable total jitter 2 4 ns t tst transmitter startup delay (tx to txo) 100 200 ns t td transmitter propagation delay (tx to txo) 35 50 ns t tr transmitter rise time C 10% to 90% (txo) 20 25 30 ns t tf transmitter fall time- 90% to 10% (txo) 20 25 30 ns t tm t tr and t tf mismatch 0.5 2 ns t ton transmit turn-on pulse width at v ts (tx) 8 20 30 ns t toff transmit turn-off pulse width at v ts (tx) 140 160 180 ns t con collision turn-on delay 700 900 ns t coff collision turn-off delay 2000 ns f cd collision frequency (cd) 8.5 10 11.5 mhz t cp collision pulse width (cd) 40 60 ns t hon cd heartbeat delay (tx to cd) 0.6 1.0 1.6 s t hw cd heartbeat duration (cd) 0.6 1.0 1.5 s t ja jabber activation delay (tx to txo off and cd) 20 60 ms t jr jabber reset unjab time (tx to txo and cd) 250 500 650 ms t ro receive off pulse width (rx+ to rx-) 200 ns downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 8 of 14 ? 2008 teridian semiconductor corporation rev 1.3 electrical specifications (continued) transmit specifications the first bit transmitted from txo may have data and phase violations. the second through last bit reproduce the tx signal with less than or equal to the specified jitter. there is no logical signal inversion between tx and txo output. a low level from tx+ to tx- results in more current flowing from the coaxial cable into the txo pin. at the end of transmission, when the transmitter changes from the enabled state to the idle state, no spurious pulses are generated, i.e., the transition on txo proceeds monotonically to zero current. receive specifications the first bit sent from rx may have data and phase violations. the second through last bit reproduce the received signal with less than or equal to the specified jitter. there is no logical signal inversion between the rxi input and the rx output. a high level at rxi produces a positive differential voltage from rx+ to rx-. figure 3: receiver timing figure 4: transmitter timing rxi t ron 50% t rd rx 50% 1st bit t rf t rr 10% 90% t ro tx txo v ts t ton t tst 90% 10% t tf 50% 90% 10% t tr t td t toff v ts 50% downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 9 of 14 ? 2008 teridian semiconductor corporation rev 1.3 figure 5: collision timing figure 6: heartbeat timing figure 7: jabber timing t con cd f cd 1 t cp t coff rxi v cd (max) v cd (min) input step function r = 1k c = 150 pf rxi rc networksimulates worst case cable step response 78q8392l collision detector cd output t hon cd tx t hw tx txo t ja cd t jr downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 10 of 14 ? 2008 teridian semiconductor corporation rev 1.3 figure 8: receive jitter timing figure 9: test loads txo input signal with 30 ns rise and fall times r = 1k ? c = 36 pf rxi rc network simulates worst case cable jitter 78q8392l receiver rx output input jitter <= 1 ns rx output jitter <= 7 ns difference <= 6 ns t rj transmitoutput (txo) 25 ? downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 11 of 14 ? 2008 teridian semiconductor corporation rev 1.3 figure 10: test circuit for tx input v ts 10 mhz 1:1 39 ? 1% tx+ tx- gnd 78q8392l/a03 39 ? 1% downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 12 of 14 ? 2008 teridian semiconductor corporation rev 1.3 caution: use handling procedures necessary for a static sensitive component. package pin designations (top view) 16-pin dip 28-pin plcc ja = 45c/w for the 28_pin plcc package 34 6 7 1110 1413 rx+ vee rx- rxivee 5 12 rr- rr+gnd 89 tx- hbe tx+ vee 12 1615 cd+ cd- cdstxo 78q8392l 1 2 3 4 282726 12 13 14 15 16 17 18 56 7 8 9 10 11 19 20 21 22 23 24 25 vee veevee vee vee vee rr- rx+ cd-cd+ cds txo n/c rxi veevee vee vee vee vee vee rx- tx+ tx- hbe gndgnd rr+ 78q8392l downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 13 of 14 ? 2008 teridian semiconductor corporation rev 1.3 mechanical drawing (inch / mm) 28-pin plcc 16-pin dip downloaded from: http:///
78q8392l/a03 low power ethernet coaxial transceiver page: 14 of 14 ? 2008 teridian semiconductor corporation rev 1.3 ordering information part description o rder number package mark 78q8392l/a03 16-pin plastic dip (lead free) 78q8392la03-cp/f 78q8392l-cp sp(date code)p3f (lot number) 78q8392l/a03 28-pin plastic plcc (lead free) 78q8392la03-28ch/f 78q8392l-28ch sp(date code)p3f (lot number) revision history rev. # date comments 1.1 december 2005 final data sheet release 1.2 january 2006 corrected package marking error (from c to p) 1.3 november, 2008 added package dimensions this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. teridian semic onductor corporation (tsc) re serves the right to make changes in specifications at any time without notice. accordingly, the r eader is cautioned to verify that the data sheet is current before placing orders. tsc assumes no liability for applications assistance. teridian semiconductor corp., 6440 oak canyon suite 100, irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http:// www.teridian.com downloaded from: http:///

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